SH7263 Datasheet, PDF (1480/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Initial
Bit
Bit Name Value R/W Description
0
OINT
0
R/(W)* Output Data FIFO Full Interrupt Request Flag
Indicates that the number of data units in the output
FIFO has become equal to or greater than the
triggering number specified by the OFTRG[1:0] bits in
the SRC output data control register (SRCODCTRL).
[Clearing conditions]
• When 0 has been written to the OINT bit after
reading OINT = 1.
• When the DMAC has transferred data from the
output FIFO resulting in the number of data units
in the FIFO being less than the specified triggering
number.
• When 1 has been written to the CL bit in
SRCCTRL.
• When 1 has been written to the SRCEN bit in
SRCCTRL while SRCEN is 0.
[Setting condition]
• When the number of data units in the output FIFO
has become equal to or greater than the specified
triggering number.
Note: * Only 0 can be written after having read as 1.
Rev. 2.00 Mar. 14, 2008 Page 1446 of 1824
REJ09B0290-0200