SH7263 Datasheet, PDF (1122/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.1 ROM-DEC Enable Control Register (CROMEN)
The ROM-DEC enable control register (CROMEN) enables subcode processing and CD-ROM
decoding, and stops CD-ROM decoding forcibly.
Bit: 7
6
5
4
SUBC_ CROM_ CROM_
EN EN STP
-
Initial value: 0
0
0
0
R/W: R/W R/W R/W R/W
3
-
0
R/W
2
-
0
R/W
1
-
0
R/W
0
-
0
R/W
Initial
Bit Bit Name Value
7
SUBC_EN 0
6
CROM_EN 0
5
CROM_STP 0
4 to 0 ⎯
All 0
R/W Description
R/W Subcode Processing Enable
This bit should be set and cleared simultaneously with
CROM_EN. It is automatically cleared when decoding
is automatically stopped due to an abnormal condition
or when CROM_STP = 1
R/W CD-ROM Decoding Enable
When this bit is set to 1, CD-ROM decoding starts after
detection of a valid sync code. When the bit is cleared
to 0, decoding stops on completion of the processing for
the sector currently being decoded.
This bit is automatically cleared when the automatic
decode-stopping function woks or when CROM_STP =
1.
R/W Forcible Stop of CD-ROM Decoding
When this bit is set to 1, CD-ROM decoding is stopped
immediately and the SUBC_EN and CROM_EN bits are
automatically reset to 0. Before decoding can resume,
this bit must be cleared to 0.
R/W Reserved
These bits are always read as 0.The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1088 of 1824
REJ09B0290-0200