SH7263 Datasheet, PDF (381/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

• Setting for Area 3
Burst read/single write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Section 9 Bus State Controller (BSC)
Access Address
H'FFFC5440
H'FFFC5460
H'FFFC5880
H'FFFC58C0
External Address Pin
H'0000440
H'0000460
H'0000880
H'00008C0
Burst read/burst write (burst length 1):
Data Bus Width
16 bits
32 bits
CAS Latency
2
3
2
3
Access Address
H'FFFC5040
H'FFFC5060
H'FFFC5080
H'FFFC50C0
External Address Pin
H'0000040
H'0000060
H'0000080
H'00000C0
Mode register setting timing is shown in figure 9.32. A PALL command (all bank pre-charge
command) is firstly issued. A REF command (auto refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the WTRP1 and WTRP0 bits in CS3WCR, are inserted between the PALL and the
first REF. Idle cycles, of which number is specified by the WTRC1 and WTRC0 bits in CS3WCR,
are inserted between REF and REF, and between the 8th REF and MRS. Idle cycles, of which
number is one or more, are inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer to the manual of the SDRAM for the idle time to be needed. When the pulse
width of the reset signal is longer than the idle time, mode register setting can be started
immediately after the reset, but care should be taken when the pulse width of the reset signal is
shorter than the idle time.
Rev. 2.00 Mar. 14, 2008 Page 347 of 1824
REJ09B0290-0200