SH7263 Datasheet, PDF (708/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 13 Watchdog Timer (WDT)
13.3.4 Notes on Register Access
The watchdog timer counter (WTCNT), watchdog timer control/status register (WTCSR), and
watchdog reset control/status register (WRCSR) are more difficult to write to than other registers.
The procedures for reading or writing to these registers are given below.
(1) Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a byte or
longword transfer instruction.
When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data,
as shown in figure 13.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the
lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or
WTCSR.
WTCNT write
15
Address: H'FFFE0002
H'5A
87
0
Write data
WTCSR write
15
Address: H'FFFE0000
H'A5
87
0
Write data
Figure 13.2 Writing to WTCNT and WTCSR
Rev. 2.00 Mar. 14, 2008 Page 674 of 1824
REJ09B0290-0200