SH7263 Datasheet, PDF (1238/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
21, 20 FIFOTRG 00
[1:0]
R/W FIFO Trigger Setting
Change the condition for generation of FLDTFIFO and
FLECFIFO transfer requests.
• In flash-memory read
00: Issue an interrupt to the CPU or issue a DMA
transfer request when FLDTFIFO stores 4 bytes of
data.
01: Issue an interrupt to the CPU or issue a DMA
transfer request when FLDTFIFO stores 16 bytes of
data.
10: Issue an interrupt request to the CPU when
FLDTFIFO stores 128 bytes of data, or issue a DMA
transfer request when FLDTFIFO stores 4 bytes of
data.
11: Issue an interrupt to the CPU when FLDTFIFO
stores 128 bytes of data, or issue a DMA transfer
request to the CPU when FLDTFIFO stores 16
bytes of data.
Note: For FLECFIFO, only FIFOTRG[0] is used.
0: Issue an interrupt to the CPU or issue a DMA transfer
request when FLECFIFO stores 4 bytes of data.
1: Issue an interrupt to the CPU or issue a DMA transfer
request when FLECFIFO stores 16 bytes of data.
• In flash-memory programming
00: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 4 bytes or more (do not set DMA
transfer).
01: Issue an interrupt to the CPU or issue a DMA
transfer request when FLDTFIFO has empty area of
16 bytes or more.
10: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 128 bytes or more (do not set DMA
transfer).
11: Issue an interrupt to the CPU when FLDTFIFO has
empty area of 128 bytes or more, or issue a DMA
transfer request when FLDTFIFO has empty area of
16 bytes or more.
Note: For FLECFIFO, only FIFOTRG[0] is used.
0: Issue an interrupt to the CPU when FLECFIFO has
empty area of 4 bytes or more (do not set DMA
transfer).
1: Issue an interrupt to the CPU or issue a DMA transfer
request when FLECFIFO has empty area of 16 bytes
or more.
Rev. 2.00 Mar. 14, 2008 Page 1204 of 1824
REJ09B0290-0200