SH7263 Datasheet, PDF (1123/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 21 CD-ROM Decoder (ROM-DEC)
21.3.2 Sync Code-Based Synchronization Control Register (CROMSY0)
The sync code-based synchronization control register (CROMSY0) selects the sync code
maintenance function.
Bit:
Initial value:
R/W:
7
SY_
AUT
1
R/W
6
SY_
IEN
0
R/W
5
SY_
DEN
0
R/W
4
-
0
R/W
3
-
1
R/W
2
-
0
R/W
1
-
0
R/W
0
-
1
R/W
Initial
Bit Bit Name Value
7
SY_AUT 1
6
SY_IEN 0
5
SY_DEN 0
4
⎯
0
3
⎯
1
R/W Description
R/W Automatic CD-ROM Sync Code Maintenance Mode
When this bit is set to 1, automatic sync maintenance
(insertion of sync codes) is applied to obtain the CD-
ROM sync codes. While this bit is set, the settings of
the SY_IEN and SY_DEN bits are invalid.
R/W Internal Sync Signal Enable
Enables the internal sync signal that is produced by the
counter in the CD-ROM decoder.
When this bit is set while SY_AUT = 0, synchronization
of the CD-ROM data is in interpolated mode, i.e. driven
by the internal counter.
R/W Synchronization with External Sync Code
Selects constant monitoring for the sync code in the
input data and bases synchronization solely on
detection of the code, regardless of the value of the
internal counter.
The setting of this bit is valid when SY_AUT = 0.
R/W Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 2.00 Mar. 14, 2008 Page 1089 of 1824
REJ09B0290-0200