SH7263 Datasheet, PDF (1792/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
35.4.16 LCDC Timing
Table 35.23 LCDC Timing
Conditions: VCC = PLLVCC = USBDVCC = 1.1 to 1.3 V, PVCC = USBDPVCC = 3.0 to 3.6 V,
AVCC = 3.0 to 3.6 V, USBAVCC = 1.1 to 1.3 V, USBAPVCC = 3.0 to 3.6 V,
VSS = PLLVSS = PVSS = AVSS = USBDVSS = USBAVSS = USBDPVSS =
USBAPVSS = 0 V, Ta = −40 to 85 °C
Item
Symbol Min.
LCD_CLK input clock frequency
tFREQ
⎯
LCD_CLK input clock rise time
tr
⎯
LCD_CLK input clock fall time
tf
⎯
LCD_CLK input clock duty
tDUTY
90
Clock (LCD_CL2) cycle time
tCC
25
Clock (LCD_CL2) high pulse width
tCHW
7
Clock (LCD_CL2) low pulse width
tCLW
7
Clock (LCD_CL2) transition time (rise/fall)
tCT
⎯
Data (LCD_DATA) delay time
tDD
−3.5
Display enable (LCD_M_DISP) delay time
tID
−3.5
Horizontal synchronous signal (LCD_CL1) delay time tHD
−3.5
Vertical synchronous signal (LCD_FLM) delay time tVD
−3.5
Max.
66.66
3
3
110
⎯
⎯
⎯
3
3
3
3
3
Unit
MHz
ns
ns
%
ns
ns
ns
ns
ns
ns
ns
ns
Figure
Figure
35.78
Rev. 2.00 Mar. 14, 2008 Page 1758 of 1824
REJ09B0290-0200