SH7263 Datasheet, PDF (1228/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3.2 Command Control Register (FLCMDCR)
FLCMDCR is a 32-bit readable/writable register that issues a command in command access mode,
specifies address issue, and specifies source or destination of data transfer. In sector access mode,
FLCMDCR specifies the number of sector transfers.
Bit: 31 30 29 28 27 26 25 24 23
ADR
CNT2
SCTCNT[19:16]
ADR
MD
CDS
RC
DOSR
-
Initial value: 0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R
22 21 20 19 18 17 16
-
SEL
RW
DOA
DR
ADRCNT[1:0]
DOC
MD2
DOC
MD1
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCTCNT[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31
ADRCNT2 0
R
Address Issue Byte Count Specification 2
Specifies the number of bytes for the address data to
be issued in address stage. This bit is used together
with ADRCNT[1:0].
0: Issue the address of byte count, specified by
ADRCNT[1:0].
1: Issue 5-byte address. ADRCNT[1:0] should be set
to 00.
30 to 27 SCTCNT All 0
[19:16]
R/W Sector Transfer Count Specification [19:16]
These bits are extended bits of the sector transfer count
specification bits (SCTCNT) 15 to 0.
SCTCNT[19:16] and SCTCNT[15:0] are used together
to operate as SCTCNT[19:0], the 20-bit counter.
Rev. 2.00 Mar. 14, 2008 Page 1194 of 1824
REJ09B0290-0200