SH7263 Datasheet, PDF (411/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Table 9.24 Number of Idle Cycles Inserted between Access Cycles to Different Memory
Types
Next Cycle
Previous Cycle SRAM
Byte Byte
SDRAM
SRAM SRAM
(Low-
Burst ROM
MPX- (BAS = (BAS =
Frequency
Burst Burst ROM
(Asynchronous) I/O 0)
1)
SDRAM Mode)
PCMCIA MPX (Synchronous)
SRAM
0
0
1
0
1
1
1.5
0
0
0
Burst ROM
0
0
(asynchronous)
1
0
1
1
1.5
0
0
0
MPX-I/O
1
1
0
1
1
1
1.5
1
1
1
Byte SRAM
0
0
(BAS = 0)
1
0
1
1
1.5
0
0
0
Byte SRAM
1
1
(BAS = 1)
2
1
0
0
1.5
1
1
1
SDRAM
1
1
2
1
0
0
⎯
1
1
1
SDRAM
1.5
1.5
(low-frequency
mode)
2.5 1.5
0.5
⎯
1
1.5
1.5 1.5
PCMCIA
0
0
1
0
1
1
1.5
0
0
0
Burst MPX
0
0
1
0
1
1
1.5
0
0
0
Burst ROM
0
0
(synchronous)
1
0
1
1
1.5
0
0
0
Figure 9.54 shows sample estimation of idle cycles between access cycles. In the actual operation,
the idle cycles may become shorter than the estimated value due to the write buffer effect or may
become longer due to internal bus idle cycles caused by stalling in the pipeline due to CPU
instruction execution or CPU register conflicts. Please consider these errors when estimating the
idle cycles.
Rev. 2.00 Mar. 14, 2008 Page 377 of 1824
REJ09B0290-0200