SH7263 Datasheet, PDF (1808/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Appendix
[Legend]
I:
Input
O: Output
H: High-level output
L:
Low-level output
Z:
High-impedance
K:
Input pins become high-impedance, and output pins retain their state.
Notes: 1. Indicates the power-on reset by low-level input to the RES pin. The pin states after a
power-on reset by the H-UDI reset assert command or WDT overflow are the same as
the initial pin states at normal operation (see section 29, Pin Function Controller (PFC)).
2. After the chip has shifted to the power-on reset state from deep standby mode by the
input on any of pins NMI, MRES, and IRQ7 to IRQ0, the pins retain the state until the
IOKEEP bit in the deep standby cancel source flag register (DSFR) is cleared (see
section 32, Power-Down Modes).
3. The week keeper circuits included in the I/O pins are turned off.
4. When pins for the connection with a crystal resonator are not used, the input pins
(EXTAL, RTC_X1, AUDIO_X1, and USB_X1) must be fixed (pulled up, pulled down,
connected to power supply, or connected to ground) and the output pins (XTAL,
RTC_X2, AUDIO_X2, and USB_X2) must be open.
5. The initial pin function depends on the data bus width of area 0 (see section 29, Pin
Function Controller (PFC)).
6. Depends on the setting of the CKOEN bit in the frequency control register (FRQCR) of
the CPG (see section 4, Clock Pulse Generator (CPG)).
7. Depends on the setting of the HIZ bit in the standby control register 3 (STBCR3) (see
section 32, Power-Down Modes).
8. Depends on the setting of the HIZMEM bit in the common control register (CMNCR) of
the BSC (see section 9, Bus State Controller (BSC)).
9. Depends on the setting of the HIZCNT bit in the common control register (CMNCR) of
the BSC (see section 9, Bus State Controller (BSC)).
10. Depends on the setting of the corresponding bit in the deep standby cancel source
select register (DSSSR) (see section 32, Power-Down Modes).
11. Depends on the setting of the RTCEN bit in the RTC control register 2 (RCR2) of the
RTC (see section 14, Realtime Clock (RTC)).
12. Depends on the AXTALE bit in the standby control register (STBCR) (see section 32,
Power-Down Modes).
13. When the CS0KEEPE bit in the deep standby control register 2 (DSCTR2) is 1, this pin
retains the state of deep standby mode. When the CS0KEEPE bit is 0, this pin enters
the state of a power-on reset (see section 32, Power-Down Modes).
14. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
15. These are the pin states in product chip mode (ASEMD = H). See the Emulation
Manual for the pin states in ASE mode (ASEMD = L).
Rev. 2.00 Mar. 14, 2008 Page 1774 of 1824
REJ09B0290-0200