SH7263 Datasheet, PDF (1269/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
25.3.1 System Configuration Control Register (SYSCFG)
SYSCFG is a register that enables high-speed operation, selects the host controller function or
function controller function, controls the DP and DM pins, controls the full-speed receiver and
controls a software reset for this module.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
-
HSE DCFM DMRPD DPRPU - FSRPC - USBE
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R R/W R R/W
Bit
Bit Name
15 to 8 ⎯
7
HSE
6
DCFM
5
DMRPD
4
DPRPU
Initial
Value
All 0
0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W High-Speed Operation Enable
0: High-speed operation is disabled
1: High-speed operation is enabled (detected by this
module)
R/W Controller Function Select
Selects the host controller function or function
controller function.
0: Function controller function is selected.
1: Host controller function is selected.
R/W D− Line Resistor Control
R/W D+ Line Resistor Control
Sets D− and D+ line resistors. Before setting these
bits, the HSE and DCFM bits should be set.
00: D− and D+ are open.
01: D− is open and D+ is pulled up.
10: D− and D+ are pulled down.
11: D− is pulled down and D+ is pulled up.
Rev. 2.00 Mar. 14, 2008 Page 1235 of 1824
REJ09B0290-0200