SH7263 Datasheet, PDF (1253/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
(2) NAND-Type Flash Memory Access
Figure 24.8 shows an example of read operation for NAND-type flash memory. In this example,
the first command is specified as H'00, address data length is specified as 3 bytes, and the number
of read bytes is specified as 8 bytes in the data counter.
CLE
ALE
WE
RE
I/O7 to I/O0
H'00
R/B
A1 A2 A3
1 2 3 4 58
Figure 24.8 Read Operation Timing for NAND-Type Flash Memory (1)
Figures 24.9 and 24.10 show examples of programming operation for NAND-type flash memory.
CLE
ALE
WE
RE
I/O7 to I/O0
H'80
R/B
A1 A2 A3
12 3458
Figure 24.9 Programming Operation Timing for NAND-Type Flash Memory (1)
Rev. 2.00 Mar. 14, 2008 Page 1219 of 1824
REJ09B0290-0200