SH7263 Datasheet, PDF (231/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 7 User Break Controller (UBC)
7.3.5 Break Bus Cycle Register (BBR)
BBR is a 16-bit readable/writable register, which specifies (1) disabling or enabling of user break
interrupt requests, (2) including or excluding of the data bus value, (3) internal CPU bus or
internal DMA bus, (4) C bus cycle or I bus cycle, (5) instruction fetch or data access, (6) read or
write, and (7) operand size as the break conditions.
Bit: 15
-
Initial value: 0
R/W: R
14 13 12 11
-
UBID DBE
-
0
0
0
0
R R/W R/W R
10 9
8
7
6
5
4
3
2
1
0
-
CP[1:0]
CD[1:0]
ID[1:0]
RW[1:0]
SZ[1:0]
0
0
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15, 14
Bit Name
⎯
13
UBID
12
DBE
11, 10 ⎯
Initial
Value
All 0
0
0
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W User Break Interrupt Disable
Disables or enables user break interrupt requests
when a break condition is satisfied.
0: User break interrupt requests enabled
1: User break interrupt requests disabled
R/W Data Break Enable
Selects whether the data bus condition is included in
the break conditions.
0: Data bus condition is not included in break
conditions
1: Data bus condition is included in break conditions
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 197 of 1824
REJ09B0290-0200