SH7263 Datasheet, PDF (153/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 5 Exception Handling
5.1.2 Exception Handling Operations
The exception handling sources are detected and start processing according to the timing shown in
table 5.2.
Table 5.2 Timing of Exception Source Detection and Start of Exception Handling
Exception
Reset
Source
Power-on reset
Manual reset
Address error
Interrupts
Register bank Bank underflow
error
Bank overflow
Instructions
Trap instruction
General illegal
instructions
Slot illegal
instructions
Integer division
exception
Timing of Source Detection and Start of Handling
Starts when the RES pin changes from low to high, when the
H-UDI reset negate command is set after the H-UDI reset
assert command has been set, or when the WDT overflows.
Starts when the MRES pin changes from low to high or when
the WDT overflows.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Detected when instruction is decoded and starts when the
previous executing instruction finishes executing.
Starts upon attempted execution of a RESBANK instruction
when saving has not been performed to register banks.
In the state where saving has been performed to all register
bank areas, starts when acceptance of register bank overflow
exception has been set by the interrupt controller (the BOVE bit
in IBNR of the INTC is 1) and an interrupt that uses a register
bank has occurred and been accepted by the CPU.
Starts from the execution of a TRAPA instruction.
Starts from the decoding of undefined code anytime except
immediately after a delayed branch instruction (delay slot)
(including FPU instructions and FPU-related CPU instructions
in FPU module standby state).
Starts from the decoding of undefined code placed directly after
a delayed branch instruction (delay slot) (including FPU
instructions and FPU-related CPU instructions in FPU module
standby state), of instructions that rewrite the PC, of 32-bit
instructions, of the RESBANK instruction, of the DIVS
instruction, or of the DIVU instruction.
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by −1.
Rev. 2.00 Mar. 14, 2008 Page 119 of 1824
REJ09B0290-0200