SH7263 Datasheet, PDF (91/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 2 CPU
2.3.3 Instruction Format
The instruction formats and the meaning of source and destination operands are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Table 2.9 Instruction Formats
Instruction Formats
0 format
15
0
xxxx xxxx xxxx xxxx
n format
15
0
xxxx nnnn xxxx xxxx
Source
Operand
—
Destination
Operand
—
—
nnnn: Register
direct
Control register or nnnn: Register
system register
direct
R0 (Register direct) nnnn: Register
direct
Control register or
system register
nnnn: Register
indirect with pre-
decrement
mmmm: Register
direct
R15 (Register
indirect with pre-
decrement)
R15 (Register
indirect with post-
increment)
nnnn: Register
direct
R0 (Register direct) nnnn: (Register
indirect with post-
increment)
Example
NOP
MOVT Rn
STS MACH,Rn
DIVU R0,Rn
STC.L SR,@-Rn
MOVMU.L
Rm,@-R15
MOVMU.L
@R15+,Rn
MOV.L R0,@Rn+
Rev. 2.00 Mar. 14, 2008 Page 57 of 1824
REJ09B0290-0200