SH7263 Datasheet, PDF (341/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Ta1
Tadw
Ta2
Ta3
T1
Tw
Twx
T2
CKIO
A25 to A0
CS5
RD/WR
AH
Read
RD
D15/D7 to D0
Write
WEn
D15/D7 to D0
WAIT
BS
Address
Address
Data
Data
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.13 Access Timing for MPX Space
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
Rev. 2.00 Mar. 14, 2008 Page 307 of 1824
REJ09B0290-0200