SH7263 Datasheet, PDF (1477/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
The number of output data units obtained as a result of conversion can be calculated by using
formulae (A) and (B) below. Table 27.4 shows the relation between the settings of the IFS and
OFS bits and the applicable formulae.
Output sampling rate
Number of output data units = Number of input data units ×
Input sampling rate
...... (A)
Output sampling rate
Number of output data units = Number of input data units ×
−1 ...... (B)
Input sampling rate
Table 27.4 Relation between Sampling Rate Settings and Number of Output Data Units
OFS Setting
(Output
Sampling 0000
Rate [kHz]) (8.0)
0 (44.1)
B
1 (48.0)
B
IFS Setting (Input Sampling Rate [kHz])
0001 0010
(11.025) (12.0)
A
A
B
A
0100
(16.0)
B
B
0101 0110
(22.05) (24.0)
A
A
B
A
1000
(32.0)
B
B
1001
(44.1)
⎯
B
1010
(48.0)
A
⎯
27.2.6 SRC Status Register (SRCSTAT)
SRCSTAT is a 16-bit readable/writable register that indicates the number of data units in the input
and output data FIFOs, whether the various interrupt sources have been generated or not, and the
flush processing status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OFDN[3:0]
IFDN[4:0]
-
-
FLF
-
OVF IINT OINT
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/(W)* R/(W)* R/(W)*
Note: * Only 0 can be written after having read as 1.
Initial
Bit
Bit Name Value R/W Description
15 to 12 OFDN[3:0] All 0
R
Output FIFO Data Count
Indicates the number of data units in the output FIFO.
11 to 7 IFDN[4:0] All 0
R
Input FIFO Data Count
Indicates the number of data units in the input FIFO.
Rev. 2.00 Mar. 14, 2008 Page 1443 of 1824
REJ09B0290-0200