SH7263 Datasheet, PDF (888/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 17 I²C Bus Interface 3 (IIC3)
(2) Transmit Operation
In transmit mode, transmit data is output from SDA, in synchronization with the fall of the transfer
clock. The transfer clock is output when MST in ICCR1 is 1, and is input when MST is 0. For
transmit mode operation timing, refer to figure 17.14. The transmission procedure and operations
in transmit mode are described below.
1. Set the ICE bit in ICCR1 to 1. Set the MST and CKS[3:0] bits in ICCR1. (Initial setting)
2. Set the TRS bit in ICCR1 to select the transmit mode. Then, TDRE in ICSR is set.
3. Confirm that TDRE has been set. Then, write the transmit data to ICDRT. The data is
transferred from ICDRT to ICDRS, and TDRE is set automatically. The continuous
transmission is performed by writing data to ICDRT every time TDRE is set. When changing
from transmit mode to receive mode, clear TRS while TDRE is 1.
SCL
SDA
(Output)
TRS
1
2
Bit 0 Bit 1
7
8
1
Bit 6 Bit 7 Bit 0
7
8
Bit 6 Bit 7
1
Bit 0
TDRE
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
User
processing
[3] Write data
to ICDRT
[2] Set TRS
[3] Write data
to ICDRT
Data 2
[3] Write data [3] Write data
to ICDRT
to ICDRT
Figure 17.14 Transmit Mode Operation Timing
Rev. 2.00 Mar. 14, 2008 Page 854 of 1824
REJ09B0290-0200