SH7263 Datasheet, PDF (937/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 18 Serial Sound Interface (SSI)
18.4.7 Serial Bit Clock Control
This function is used to control and select which clock is used for the serial bus interface.
If the serial clock direction is set to input (SCKD = 0), the SSI module is in clock slave mode and
the shift register uses the bit clock that was input to the SSISCK pin.
If the serial clock direction is set to output (SCKD = 1), the SSI module is in clock master mode,
and the shift register uses the oversampling clock, or the bit clock that is generated by dividing it.
The oversampling clock is then divided by the ratio in the serial oversampling clock divide ratio
bit (CKDV) in SSICR and used as the bit clock in the shift register.
In either case the module pin, SSISCK, is the same as the bit clock.
Rev. 2.00 Mar. 14, 2008 Page 903 of 1824
REJ09B0290-0200