SH7263 Datasheet, PDF (966/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit10:
TST2
0
0
0
0
1
1
1
1
Bit9:
TST1
0
0
1
1
0
0
1
1
Bit8:
TST0
0
1
0
1
0
1
0
1
Description
Normal Mode (initial value)
Listen-Only Mode (Receive-Only Mode)
Self Test Mode 1 (External)
Self Test Mode 2 (Internal)
Write Error Counter
Error Passive Mode
Setting prohibited
Setting prohibited
Bit 7 — Auto-wake Mode (MCR7): MCR7 enables or disables the Auto-wake mode. If this bit is
set, the RCAN-TL1 automatically cancels the sleep mode (MCR5) by detecting CAN bus activity
(dominant bit). If MCR7 is cleared the RCAN-TL1 does not automatically cancel the sleep mode.
RCAN-TL1 cannot store the message that wakes it up.
Note: This bit can be modified only Reset or Halt mode.
Bit7: MCR7
0
1
Description
Auto-wake by CAN bus activity disabled (Initial value)
Auto-wake by CAN bus activity enabled
Bit 6 — Halt during Bus Off (MCR6): MCR6 enables or disables entering Halt mode
immediately when MCR1 is set during Bus Off. This bit can be modified only in Reset or Halt
mode. Please note that when Halt is entered in Bus Off the CAN engine is also recovering
immediately to Error Active mode.
Bit6: MCR6
0
1
Description
If MCR[1] is set, RCAN-TL1 will not enter Halt mode during Bus Off but wait
up to end of recovery sequence (Initial value)
Enter Halt mode immediately during Bus Off if MCR[1] or MCR[14] are
asserted.
Rev. 2.00 Mar. 14, 2008 Page 932 of 1824
REJ09B0290-0200