SH7263 Datasheet, PDF (1763/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

CKIO
A25 to A0
A12/A11^*1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
D31 to D0
Tp
Tpw
Trr
t_AD3
t_AD3
t_AD3
t_AD3
t_CSD2
t_CSD2
t_CSD2
t_CSD2
t_RWD2
t_RWD2
t_RASD2
t_RASD2
t_RASD2
t_RASD2
t_CASD2
t_CASD2
t_CASD2
t_DQMD2
(Hi-Z)
Section 35 Electrical Characteristics
Trc
Trc
Trc
BS
CKE
t_CKED2
t_CKED2
DACKn
TENDn ^*2
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 35.40 Synchronous DRAM Self-Refreshing Timing in Low-Frequency Mode
(WTRP = 2 Cycles)
Rev. 2.00 Mar. 14, 2008 Page 1729 of 1824
REJ09B0290-0200