SH7263 Datasheet, PDF (1390/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Received token
Buffer A
Empty
Writing
Buffer B
Sent packet
IN
IN
Writing ended
Empty
Null
Null
IN
Transfer enabled
Empty
Data-A
SOF packet
Buffer A
Buffer B
Empty
Writing Writing ended
Empty
Writing
Transfer enabled
Writing ended
Received token
Buffer A
Buffer B
Sent packet
IN
Empty
Writing Writing ended
Empty
Writing
Null
IN
Transfer
enabled
Empty
Writing ended
Data-A
IN
Writing
Writing ended
Transfer
enabled
Empty
Data-B
Received token
Buffer A
Buffer B
Sent packet
IN
Empty
Writing Writing ended
Empty
Writing
Null
IN
IN
IN
Transfer
enabled
Empty
Writing ended
Writing
Writing ended
Transfer
enabled
Empty
Data-A
Null
Data-B
Figure 25.17 Example of Data Setup Function Operation
(5) Isochronous Transfer Transmission Buffer Flush when the Function Controller
Function is Selected
If an SOF packet or a μSOF packet is received without receiving an IN token in the interval frame
during isochronous data transmission, this module operates as if an IN token had been corrupted,
and clears the buffer for which transmission is enabled, putting that buffer in the writing enabled
state.
If a double buffer is being used and writing to both buffers has been completed, the buffer
memory that was cleared is seen as the data having been sent at the same interval frame, and
transmission is enabled for the buffer memory that is not discarded with SOF or μSOF packets
reception.
The timing at which the operation of the buffer flush function varies depending on the value set
for the IITV bit.
Rev. 2.00 Mar. 14, 2008 Page 1356 of 1824
REJ09B0290-0200