SH7263 Datasheet, PDF (1754/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Td1
Td2
Td3
Td4
Tc1
Tc2
Tc3
Tc4
Tde
t_AD1
t_AD1
t_AD1
Column
address
t_AD1
READ command
t_AD1
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
DQMxx
t_CSD1
t_RWD1
t_RASD1
t_CASD1
t_DQMD1
t_CSD1
t_RWD1
t_CASD1
t_DQMD1
D31 to D0
t_BSD
BS
t_RDS2
t_RDH2
t_BSD
t_RDS2 t_RDH2
CKE
DACKn
TENDn*²
t_DACD
(High)
t_DACD
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 35.31 Synchronous DRAM Burst Read Bus Cycle (Four Read Cycles)
(Bank Active Mode: READ Command, Same Row Address, CAS Latency 2, WTRCD = 0 Cycle)
Rev. 2.00 Mar. 14, 2008 Page 1720 of 1824
REJ09B0290-0200