SH7263 Datasheet, PDF (965/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
MCR15 (ID Reorder) = 0
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
H'100 + N*32
0
STDID[10:0]
RTR IDE EXTID[17:16]
H'102 + N*32
H'104 + N*32
0
H'106 + N*32
EXTID[15:0]
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
0
IDE_ EXTID_LAFM
LAFM [17:16]
MCR15 (ID Reorder) = 1
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
H'100 + N*32 IDE RTR 0
STDID[10:0]
EXTID[17:16]
H'102 + N*32
H'104 + N*32
IDE_
LAFM
0
0
H'106 + N*32
EXTID[15:0]
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
EXTID_LAFM
[17:16]
Word/LW
Word
Word/LW
Word
Word/LW
Word
Word/LW
Word
Control 0
LAFM Field
Control 0
LAFM Field
Figure 19.10 ID Reorder
This bit can be modified only in reset mode.
Bit 14 — Auto Halt Bus Off (MCR14): If both this bit and MCR6 are set, MCR1 is
automatically set as soon as RCAN-TL1 enters BusOff.
Bit14: MCR14
0
1
Description
RCAN-TL1 remains in BusOff for normal recovery sequence (128 x 11
Recessive Bits) (Initial value)
RCAN-TL1 moves directly into Halt Mode after it enters BusOff if MCR6 is
set.
This bit can be modified only in reset mode.
Bit 13 — Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 12 — Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 11 — Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 10 - 8 — Test Mode (TST[2:0]): This bit enables/disables the test modes. Please note that
before activating the Test Mode it is requested to move RCAN-TL1 into Halt mode or Reset
mode. This is to avoid that the transition to Test Mode could affect a transmission/reception in
progress. For details, please refer to section 19.4.1, Test Mode Settings.
Please note that the test modes are allowed only for diagnosis and tests and not when RCAN-TL1
is used in normal operation.
Rev. 2.00 Mar. 14, 2008 Page 931 of 1824
REJ09B0290-0200