SH7263 Datasheet, PDF (1002/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
Bit 11 — TCMR1 compare match enable: When this bit is set, IRR15 is set by TCMR1
compare match.
Bit11 TTCR0 11
0
1
Description
IRR15 isn't set by TCMR1 compare match (initial value)
IRR15 is set by TCMR1 compare match
Bit 10 — TCMR0 compare match enable: When this bit is set, IRR14 is set by TCMR0
compare match.
Bit10 TTCR0 10
0
1
Description
IRR14 isn't set by TCMR0 compare match (initial value)
IRR14 is set by TCMR0 compare match
Bits 9 to 7: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bit 6 — Timer Clear-Set Control by TCMR0: Specifies if the Timer is to be cleared and set to
H'0000 when the TCMR0 matches to the TCNTR. Please note that the TCMR0 is also capable to
generate an interrupt signal to the CPU via IRR14.
Note: If RCAN-TL1 is working in TTCAN mode (CMAX isn't 3'b111), TTCR0 bit6 has to be
‘0’ to avoid clearing Local Time.
Bit6: TTCR0 6
0
1
Description
Timer is not cleared by the TCMR0 (initial value)
Timer is cleared by the TCMR0
Rev. 2.00 Mar. 14, 2008 Page 968 of 1824
REJ09B0290-0200