SH7263 Datasheet, PDF (316/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Bit
15, 14
13
12
11
Bit Name
⎯
DEEP
SLOW
RFSH
Initial
Value
All 0
0
0
0
R/W Description
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RFSH or
RMODE bit is set to 1 while this bit is set to 1, the deep
power-down entry command is issued and the low-
power SDRAM enters the deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
R/W Low-Frequency Mode
Specifies the output timing of command, address, and
write data for SDRAM and the latch timing of read
data from SDRAM. Setting this bit makes the hold time
for command, address, write and read data extended
for half cycle (output or read at the falling edge of
CKIO). This mode is suitable for SDRAM with low-
frequency clock.
0: Command, address, and write data for SDRAM is
output at the rising edge of CKIO. Read data from
SDRAM is latched at the rising edge of CKIO.
1: Command, address, and write data for SDRAM is
output at the falling edge of CKIO. Read data from
SDRAM is latched at the falling edge of CKIO.
R/W Refresh Control
Specifies whether or not the refresh operation of the
SDRAM is performed.
0: No refresh
1: Refresh
Rev. 2.00 Mar. 14, 2008 Page 282 of 1824
REJ09B0290-0200