SH7263 Datasheet, PDF (1213/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 23 D/A Converter (DAC)
23.3 Register Descriptions
The D/A converter has the following registers.
Table 23.2 Register Configuration
Register Name
D/A data register 0
D/A data register 1
D/A control register
Abbreviation R/W
DADR0
R/W
DADR1
R/W
DACR
R/W
Initial
Value
H'00
H'00
H'1F
Address
H'FFFE6800
H'FFFE6801
H'FFFE6802
Access
Size
8, 16
8, 16
8, 16
23.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)
DADR is an 8-bit readable/writable register that stores data to which D/A conversion is to be
performed. Whenever analog output is enabled, the values in DADR are converted and output to
the analog output pins.
DADR is initialized to H'00 by a power-on reset or in module standby mode.
Bit: 7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W
Rev. 2.00 Mar. 14, 2008 Page 1179 of 1824
REJ09B0290-0200