SH7263 Datasheet, PDF (1287/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
7
DEZPM
0
R/W Zero-Length Packet Added Mode
This bit is valid when the transmitting direction
(reading from the buffer memory) has been set for
the pipe specified by the CURPIPE bits.
0: No packet is added.
1: A packet is added.
6 to 3 _⎯
All 0 R/W
2 to 0 CURPIPE[2:0] 000 R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
FIFO Port Access Pipe Specification*²
000: Not specified
001: PIPE1
010 PIPE2
011: PIPE3
100: PIPE4
101: PIPE5
110: PIPE6
111: PIPE7
Notes: 1. Only reading 0 and writing 1 are valid.
2. Changing the values of the CURPIPE bits in succession requires an access cycle
lasting a minimum of 120 ns plus five bus cycles.
25.3.8 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR)
CFIFOCTR, D0FIFOCTR and D1FIFOCTR are registers that determine whether or not writing to
the buffer memory has been finished, the buffer in the CPU has been cleared, and the FIFO port is
accessible. CFIFOCTR, D0FIFOCTR, and D1FIFOCTR are used for the corresponding FIFO
ports.
These registers are initialized by a power-on reset or a software reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BVAL BCLR FRDY -
DTLN[11:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W*¹ R/W*² R
R
R
R
R
R
R
R
R
R
R
R
R
R
Rev. 2.00 Mar. 14, 2008 Page 1253 of 1824
REJ09B0290-0200