SH7263 Datasheet, PDF (183/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 6 Interrupt Controller (INTC)
6.3.4 Interrupt Control Register 2 (ICR2)
ICR2 is a 16-bit register that specifies the detection mode for external interrupt input pins PINT7
to PINT0 individually: low level or high level.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- PINT7S PINT6S PINT5S PINT4S PINT3S PINT2S PINT1S PINT0S
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
15 to 8
Bit Name
⎯
7
PINT7S
6
PINT6S
5
PINT5S
4
PINT4S
3
PINT3S
2
PINT2S
1
PINT1S
0
PINT0S
[Legend]
n = 7 to 0
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value
should always be 0.
R/W PINT Sense Select
R/W These bits select whether interrupt signals
R/W
corresponding to pins PINT7 to PINT0 are detected by
a low level or high level.
R/W _{0: Interrupt request is detected on low level of PINTn}
R/W input
R/W 1: Interrupt request is detected on high level of PINTn
R/W
input
R/W
Rev. 2.00 Mar. 14, 2008 Page 149 of 1824
REJ09B0290-0200