SH7263 Datasheet, PDF (1262/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.6 DMA Transfer Specifications
The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 24.6 summarizes DMA transfer enable or disable states in each access
mode.
Table 24.6 DMA Transfer Specifications
FLDTFIFO
FLECFIFO
Sector Access Mode
DMA transfer enabled
DMA transfer enabled
Command Access Mode
DMA transfer enabled
DMA transfer disabled
In little endian form, these bits should not be used because a 16-byte DMA transfer causes a data
replacement in longword units.
For details on DMAC settings, see section 10, Direct Memory Access Controller (DMAC).
Rev. 2.00 Mar. 14, 2008 Page 1228 of 1824
REJ09B0290-0200