SH7263 Datasheet, PDF (1083/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 20 IEBus^TM Controller (IEB)
Initial
Bit
Bit Name Value R/W Description
0
GG
0
R
General Broadcast Reception Acknowledgement
Set to 1 when the slave address is acknowledged as
H'FFF in broadcast reception. Like the receive
broadcast bit, this flag is valid when the slave/broadcast
reception is started. (This flag is changed at the time of
setting the RXS flag in IERSR.)
The previous value remains unchanged until the next
slave/broadcast reception is started. This flag is cleared
to 0 in slave normal reception.
0: (1) A unit is in slave reception
(2) When H'FFF is not acknowledged in the slave
address field in broadcast reception
1: When H'FFF is acknowledged in the slave address
field in broadcast reception
20.3.16 IEBus Transmit Status Register (IETSR)
IETSR detects events such as transmit start, transmit normal completion, and transmit error end.
Each status flag in IETSR corresponds to a bit in the IEBus transmit interrupt enable register
(IEIET) that enables or disables each interrupt. This register is cleared by writing 1 to each bit.
Bit:
Initial value:
R/W:
7
6
5
4
3
2
1
0
-
TXS
TXF
-
TXEAL TXETTME TXERO TXEACK
0
0
0
0
0
0
0
0
R R/(W)* R/(W)* R R/(W)* R/(W)* R/(W)* R/(W)*
Initial
Bit
Bit Name Value R/W Description
7
⎯
0
⎯
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1049 of 1824
REJ09B0290-0200