SH7263 Datasheet, PDF (1272/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
1, 0
LNST[1:0] *
R
USB Data Line Status
Table 25.3 shows the USB data bus line status. The
line status (D+ and D− lines) of the USB data bus is
monitored using the setting of these bits.
The line status can be confirmed with the full-speed
receiver. This module automatically controls the full-
speed receiver by supplying USBCLK. However, the
full-speed receiver can be enabled using software,
without supplying USBCLK, by setting the FSRPC bit
in SYSCFG. After a power-on reset, D+ and D− line
status can be confirmed prior to the USBCLK supply
by setting the FSRPC bit to 1.
Once USBCLK is supplied, software setting is not
required.
Note: * Depending on the D+ and D− line status.
Table 25.3 USB Data Bus Line Status
LNST[1]
LNST[0]
During Full-Speed During High-Speed During Chirp
Operation
Operation
Operation
0
0
SE0
Squelch
Squelch
0
1
J state
Not squelch
Chirp J
1
0
K state
Invalid
Chirp K
1
1
SE1
Invalid
Invalid
[Legend]
Chirp:
The reset handshake protocol is being executed in high-speed operation enabled
state (the HSE bit in SYSCFG is set to 1).
Squelch: SE0 or idle state
Not squelch: High-speed J state or high-speed K state
Chirp J:
Chirp J state
Chirp K:
Chirp K state
Rev. 2.00 Mar. 14, 2008 Page 1238 of 1824
REJ09B0290-0200