SH7263 Datasheet, PDF (1254/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
CLE
ALE
WE
RE
I/O7 to I/O0
H'10
R/B
H'70
Status
Figure 24.10 Programming Operation Timing for NAND-Type Flash Memory (2)
(3) NAND-Type Flash Memory (2048 + 64 Bytes) Access
Figure 24.11 shows an example of read operation for NAND-type flash memory (2048 + 64
bytes). In this example, the first command is specified as H'00, the second command is specified
as H'30, and address data length is specified as 4 bytes. The number of read bytes is specified as 4
bytes in the data counter.
CLE
ALE
WE
RE
H'00
H'30
I/O7 to I/O0
A1 A2 A3 A4
1234
R/B
Figure 24.11 Read Operation Timing for NAND-Type Flash Memory
Rev. 2.00 Mar. 14, 2008 Page 1220 of 1824
REJ09B0290-0200