SH7263 Datasheet, PDF (1418/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 26 LCD Controller (LCDC)
26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR)
LDHSYNR specifies the timing of the generation of the horizontal (scan direction) sync signals
for the LCD module.
Bit: 15 14 13 12 11 10 9
HSYNW HSYNW HSYNW HSYNW
3
2
1
0
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R
R
R
8
7
6
5
4
3
2
1
0
-
HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP HSYNP
7
6
5
4
3
2
1
0
0
0
1
0
1
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15
HSYNW3 0
R/W Horizontal Sync Signal Width
14
HSYNW2 0
R/W Set the width of the horizontal sync signals (CL1 and
13
HSYNW1 0
R/W ^{Hsync) (unit: character = 8 dots).}
12
HSYNW0 0
R/W ^{Specify to the value of (the number of horizontal sync}
signal width) -1.
Example: For a horizontal sync signal width of 8 dots.
HSYNW = (8 dots/8 dots/character) -1 = 0 =
H'0
11 to 8 ⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
HSYNP7 0
R/W Horizontal Sync Signal Output Position
6
HSYNP6 1
R/W Set the output position of the horizontal sync signals
5
HSYNP5 0
R/W ^{(unit: character = 8 dots).}
4
HSYNP4 1
R/W ^{Specify to the value of (the number of horizontal sync}
signal output position) -1.
3
HSYNP3 0
R/W
Example: For a LCD module with a width of 640 pixels.
2
HSYNP2 0
R/W
HSYNP = [(640/8) +1] -1 = 80 = H'50
1
HSYNP1 0
R/W
In this case, the horizontal sync signal is
0
HSYNP0 0
R/W
active from the 648th through the 655th dot.
Note: The following conditions must be satisfied:
HTCN ≥ HSYNP+HSYNW+1
HSYNP ≥ HDCN+1
Rev. 2.00 Mar. 14, 2008 Page 1384 of 1824
REJ09B0290-0200