SH7263 Datasheet, PDF (452/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
(3) On-Chip Peripheral Module Request
In this mode, the transfer is performed in response to the DMA transfer request signal from an on-
chip peripheral module.
Table 10.8 lists the DMA transfer request signals sent from on-chip peripheral modules to DMAC.
If DMA transfer is enabled (DE = 1, DME = 1, TEMASK = 0 or 1 (TE = 0 when TEMASK = 0),
AE = 0, and NMIF = 0) in on-chip peripheral module request mode, DMA transfer is started by a
transfer request signal.
In on-chip peripheral module request mode, there are cases where transfer source or destination is
fixed. For details, see table 10.8.
Table 10.8 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR DMARS DMA Transfer
Request
RS[3:0] MID RID Source
Transfer
DMA Transfer Request Signal Source
1001 Any
Any RCAN-TL10
reception
DM0 (reception end)
RCAN0
MB0
1010 Any
Any RCAN-TL11
reception
DM0 (reception end)
RCAN1
MB0
1000 000000 11 USB
USB_DMA0
(receive FIFO full)
D0FIFO
USB_DMA0
Any
(transmit FIFO empty)
000001 11 USB
USB_DMA1
(reception FIFO full)
D1FIFO
USB_DMA1
Any
(transmission FIFO empty)
000100 01 SDHI
transmission
TXI (transmission data empty) Any
10 SDHI
reception
RXI (reception data full)
Data
register
Transfer Bus
Destination Mode
Any
Cycle
steal
Any
Any
D0FIFO
Cycle
steal or
burst
Any
D1FIFO
Data
register
Any
Cycle
steal
Rev. 2.00 Mar. 14, 2008 Page 418 of 1824
REJ09B0290-0200