SH7263 Datasheet, PDF (1815/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
4.3 Clock Operating
Modes
Table 4.3 Relationship
between Clock
Operating Mode and
Frequency Range
Page
106
4.5.1 Changing the
112
Multiplication Rate
4.5.3 Note on Using a 114
PLL Oscillation Circuit
Revision (See Manual for Details)
Table amended
Clock
Operating FRQCR
Mode
Setting*¹
0
H'x003
H'x004
H'x005
H'x006
H'x104
H'x106
1
H'x003
H'x004
H'x005
H'x006
H'x104
H'x106
2
H'x003
H'x004
H'x005
H'x006
H'x104
H'x106
PLL
Frequency
Multiplier
PLL
Circuit
Ratio of
Internal Clock
Frequencies
(I:B:P)*²
Input Clock*³
Selectable Frequency Range (MHz)
Output Clock Internal Clock
Peripheral
(CKIO Pin)
(Iφ)
Bus Clock (Bφ) Clock (Pφ)
ON (× 8)
8:4:2
10 to 16.67
40 to 66.66
80 to 133.36 40 to 66.66
20 to 33.33
ON (× 8)
8:4:4/3
10 to 16.67
40 to 66.66
80 to 133.36 40 to 66.66
13.33 to 22.22
ON (× 8)
8:4:1
10 to 16.67
40 to 66.66
80 to 133.36 40 to 66.66
10 to 16.67
ON (× 8)
8:4:2/3
10 to 16.67
40 to 66.66
80 to 133.36 40 to 66.66
6.67 to 11.11
ON (× 12) 12:4:2
10 to 16.67
40 to 66.66
120 to 200
40 to 66.66
20 to 33.33
ON (× 12)
ON (× 8)
12:4:1
4:2:1
10 to 16.67
20 to 33.33
40 to 66.66
40 to 66.66
120 to 200
80 to 133.36
40 to 66.66
40 to 66.66
10 to 16.67
20 to 33.33
ON (× 8)
4:2:2/3
20 to 33.33
40 to 66.66
80 to 133.36 40 to 66.66
13.33 to 22.22
ON (× 8)
4:2:1/2
20 to 33.33
40 to 66.66
80 to 133.36 40 to 66.66
10 to 16.67
ON (× 8)
4:2:1/3
20 to 33.33
40 to 66.66
80 to 133.36 40 to 66.66
6.67 to 11.11
ON (× 12) 6:2:1
20 to 33.33
40 to 66.66
120 to 200.0 40 to 66.66
20 to 33.33
ON (× 12)
ON (× 8)
6:2:1/2
2:1:1/2
20 to 33.33
40 to 66.66
40 to 66.66
⎯
120 to 200.0
80 to 133.36
40 to 66.66
40 to 66.66
10 to 16.67
20 to 33.33
ON (× 8)
2:1:1/3
40 to 66.66
⎯
80 to 133.36 40 to 66.66
13.33 to 22.22
ON (× 8)
2:1:1/4
40 to 66.66
⎯
80 to 133.36 40 to 66.66
10 to 16.67
ON (× 8)
2:1:1/6
40 to 66.66
⎯
80 to 133.36 40 to 66.66
6.67 to 11.11
ON (× 12) 3:1:1/2
40 to 66.66
⎯
120 to 200.0 40 to 66.66
20 to 33.33
ON (× 12) 3:1:1/4
40 to 66.66
⎯
120 to 200.0 40 to 66.66
10 to 16.67
Description amended
Oscillation settling time must be provided when the
multiplication rate of the PLL circuit is changed. The on-chip
WDT counts the settling time. The oscillation settling time is the
same as when software standby mode is canceled.
Description deleted
In the PLLVcc and PLLVss connection pattern for the PLL,
signal lines from the board power supply pins must be as short
as possible and pattern width must be as wide as possible to
reduce inductive interference.
4.6 Notes on Board ⎯
Design
Since the analog power supply pins of the PLL are sensitive to
the noise, the system may malfunction due to inductive
interference at the other power supply pins. To prevent such
malfunction, the analog power supply pin Vcc and digital power
supply pin PVcc should not supply the same resources on the
board if at all possible.
Deleted
Rev. 2.00 Mar. 14, 2008 Page 1781 of 1824
REJ09B0290-0200