SH7263 Datasheet, PDF (1851/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Notes on display-off mode
(LCDC stopped) ................................... 1418
NRDY interrupt .................................... 1313
NYET handshake responses ................. 1349
O
Offset error ........................................... 1172
On-chip peripheral module interrupts..... 158
On-chip peripheral module request......... 418
Operation for hardware rotation ........... 1418
Operation in asynchronous mode ........... 758
Operation in clocked synchronous
mode ....................................................... 769
Output load circuit ................................ 1766
P
Package dimensions.............................. 1777
Page conflict ......................................... 1549
PCMCIA interface .................................. 359
Permissible signal source impedance ... 1175
Phase counting mode .............................. 537
Pin function controller (PFC) ............... 1455
Pin states of this LSI ............................. 1771
PINT interrupts ....................................... 157
Pipe control........................................... 1322
Pipe schedule ........................................ 1360
PLL circuit.............................................. 101
Power-down mode.................................. 345
Power-down modes .............................. 1551
Power-down state ..................................... 85
Power-on reset ........................................ 124
Power-on sequence ................................. 346
Power-supply control sequences........... 1413
Prefetch operation
(only for operand cache)......................... 222
Procedure register (PR)............................. 44
Processing of analog input pins ............ 1174
Program counter (PC) ............................... 44
Program execution state............................ 85
PWM Modes........................................... 532
Q
Quantization error ................................. 1172
R
RCAN-TL1 control registers .................. 930
RCAN-TL1 interrupt sources................ 1005
RCAN-TL1 mailbox registers................. 951
RCAN-TL1 memory map ....................... 912
RCAN-TL1 timer registers ..................... 966
RCAN-TL1 timing................................ 1748
Realtime clock (RTC) ............................. 683
Receive data sampling timing and
receive margin (asynchronous mode) ..... 779
Reconfiguration of mailbox .................. 1003
Register addresses
(by functional module, in order of the
corresponding section numbers) ........... 1602
Register bank error exception
handling .......................................... 129, 184
Register bank errors ................................ 129
Register bank exception .......................... 184
Register banks................................... 45, 180
Register bits .......................................... 1629
Register states in each operating
mode ..................................................... 1680
Registers
ABACK0 ............................................ 959
ABACK1 ............................................ 959
ADCSR ............................................. 1156
ADDRA to ADDRH ......................... 1155
BAMR................................................. 194
BAR .................................................... 193
BBR .................................................... 197
BCR0 .................................................. 940
BCR1 .................................................. 938
BDMR................................................. 196
BDR .................................................... 195
BEMPENB........................................ 1265
BEMPSTS......................................... 1276
BRCR.................................................. 199
Rev. 2.00 Mar. 14, 2008 Page 1817 of 1824
REJ09B0290-0200