SH7263 Datasheet, PDF (1275/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
Initial
Bit
Bit Name
Value R/W Description
5
RESUME
0
R/W Resume Output
Outputs a resume signal to the USB bus by setting
this bit to 1.
0: Resume signal output is stopped.
1: Resume signal is output.
4
UACT
0
R/W USB Bus Enable
Controls the SOF or μSOF packet transmission to
the USB bus. SOF packet transmission intervals are
controlled by this module. When a 0 is written to this
bit, a transition will be made to the bus idle state after
the next SOF is transmitted.
0: Down port is disabled (SOF/μSOF transmission is
disabled).
1: Down port is enabled (SOF/μSOF transmission is
enabled).
3, 2
⎯
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 2.00 Mar. 14, 2008 Page 1241 of 1824
REJ09B0290-0200