SH7263 Datasheet, PDF (147/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 4 Clock Pulse Generator (CPG)
4.5.2 Changing the Division Ratio
Counting by the WDT does not proceed if the frequency divisor is changed but the multiplier is
not.
1. In the initial state, IFC = B'0 and PFC[2:0] = B'011.
2. Set the desired value in the IFC and PFC2 to IFC0 bits. The values that can be set are limited
by the clock operating mode and the multiplication rate of PLL circuit. Note that if the wrong
value is set, this LSI will malfunction.
3. After the register bits (IFC and PFC2 to PFC0) have been set, the clock is supplied of the new
division ratio.
Notes: 1. When executing the SLEEP instruction after the frequency has been changed, be sure
to read the frequency control register (FRQCR) three times before executing the
SLEEP instruction.
2. When the frequency-multiplier of the PLL circuit is changed and while oscillation is
settling after exit from software standby mode, an unstable CKIO clock will be output
in clock mode 0, 1, or 3. Control bits 14, 13, and 12 in FRQCR to ensure that this
unstable CKIO clock does not lead to malfunctions.
Rev. 2.00 Mar. 14, 2008 Page 113 of 1824
REJ09B0290-0200