SH7263 Datasheet, PDF (1593/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 32 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
2
MSTP32 1
R/W Module Stop 32
When the MSTP32 bit is set to 1, the supply of the
clock to the ADC is halted.
0: ADC runs.
1: Clock supply to ADC is halted.
1
MSTP31 1
R/W Module Stop 31
When the MSTP31 bit is set to 1, the supply of the
clock to the DAC is halted.
0: DAC runs.
1: Clock supply to DAC is halted.
0
MSTP30 0
R/W Module Stop 30
When the MSTP30 bit is set to 1, the supply of the
clock to the RTC is halted.
0: RTC runs.
1: Clock supply to RTC is halted.
32.2.4 Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes. Only byte access is valid.
Note: When writing to this register, see section 32.4, Usage Notes.
Bit: 7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP
47
46
45
44
-
MSTP MSTP MSTP
42
41
40
Initial value: 1
1
1
1
1
1
1
1
R/W: R/W R/W R/W R/W R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7
MSTP47 1
R/W Module Stop 47
When the MSTP47 bit is set to 1, the supply of the
clock to the SCIF0 is halted.
0: SCIF0 runs.
1: Clock supply to SCIF0 is halted.
Rev. 2.00 Mar. 14, 2008 Page 1559 of 1824
REJ09B0290-0200