SH7263 Datasheet, PDF (993/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 19 Controller Area Network (RCAN-TL1)
(4) Abort Acknowledge Register (ABACK1, ABACK0)
The ABACK1 and ABACK0 are 16-bit read/conditionally-write registers. These registers are used
to signal to the CPU that a mailbox transmission has been aborted as per its request. When an
abort has succeeded the RCAN-TL1 sets the corresponding bit in the ABACK register. The CPU
may clear the Abort Acknowledge bit by writing a ‘1’ to the corresponding bit location. Writing a
‘0’ has no effect. An ABACK bit position is set by the RCAN-TL1 to acknowledge that a TXPR
bit has been cleared by the corresponding TXCR bit.
• ABACK1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ABACK1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note: * Only when writing a ‘1’ to clear.
Bit 15 to 0 — Notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 0 corresponds to Mailbox-31 to 16 respectively.
Bit[15:0]:ABACK1 Description
0
[Clearing Condition] Writing ‘1’ (Initial value)
1
Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition]
Completion of transmission cancellation for corresponding mailbox
• ABACK0
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
ABACK0[15:1]
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R
Note: * Only when writing a ‘1’ to clear.
Bit 15 to 1 — Notifies that the requested transmission cancellation of the corresponding Mailbox
has been performed successfully. The bit 15 to 1 corresponds to Mailbox-15 to 1 respectively.
Rev. 2.00 Mar. 14, 2008 Page 959 of 1824
REJ09B0290-0200