SH7263 Datasheet, PDF (1241/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
6
TRREQF1 0
R/(W)* FLECFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLECFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
FLECFIFO
1: Indicates that a transfer request is issued from
FLECFIFO
5
TRREQF0 0
R/(W)* FLDTFIFO Transfer Request Flag
Indicates that a transfer request is issued from
FLDTFIFO.
This bit is a flag. 1 cannot be written to this bit. Only 0
can be written to clear the flag.
0: Indicates that no transfer request is issued from
FLDTFIFO
1: Indicates that a transfer request is issued from
FLDTFIFO
4
STERINTE 0
R/W Interrupt Enable at Status Error
Enables or disables an interrupt request to the CPU
when a status error has occurred.
0: Disables the interrupt request to the CPU by a status
error
1: Enables the interrupt request to the CPU by a status
error
3
RBERINTE 0
RW Interrupt Enable at R/B Timeout Error
Enables or disables an interrupt request to the CPU
when an R/B timeout error has occurred.
0: Disables the interrupt request to the CPU by an R/B
timeout error
1: Enables the interrupt request to the CPU by an R/B
timeout error
Rev. 2.00 Mar. 14, 2008 Page 1207 of 1824
REJ09B0290-0200