SH7263 Datasheet, PDF (1816/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Main Revisions for this Edition
Item
5.1.2 Exception
Handling Operations
Table 5.2 Timing of
Exception Source
Detection and Start of
Exception Handling
Page Revision (See Manual for Details)
119, 120 Table amended
Exception
Instructions
Source
Integer division
exception
FPU exception
Timing of Source Detection and Start of Handling
Starts when detecting division-by-zero exception or overflow
exception caused by division of the negative maximum value
(H'80000000) by −1.
Starts when detecting invalid operation exception defined by
IEEE standard 754, division-by-zero exception, overflow,
underflow, or inexact exception.
Also starts when qNaN or ±∞ is input to the source for a floating
point operation instruction when the QIS bit in FPSCR is set.
5.3.1 Address Error 127
Sources
Table 5.7 Bus Cycles
and Address Errors
5.3.2 Address Error 128
Exception Handling
5.6.1 Types of
133
Exceptions Triggered by
Instructions
Table 5.10 Types of
Exceptions Triggered by
Instructions
Table amended
Type
Bus Cycle
Bus
Master
Data
read/write
CPU or
DMAC
Bus Cycle Description
Word data accessed from even address
Word data accessed from odd address
Longword data accessed from a longword
boundary
Longword data accessed from other than a
long-word boundary
Double longword data accessed from a
double longword boundary
Double longword data accessed from other
than a double longword boundary
Byte or word data accessed in on-chip
peripheral module space*
Address Errors
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Address error occurs
None (normal)
Description amended and note added
When an address error occurs, the bus cycle in which the
address error occurred ends.* When the executing instruction
then finishes, address error exception handling starts. …
Note: * In the case of an address error caused by a data
read or write, if the address error is caused by an
instruction fetch and the bus cycle in which the
address error occurred has not ended by the end of
the above operation, the CPU restarts address
error exception handling before the bus cycle ends.
Description amended
Exception handling can be triggered by trap instructions, slot
illegal instructions, general illegal instructions, integer division
exceptions, and FPU exceptions, as shown in table 5.10.
Table amended
Type
FPU exceptions
Source Instruction
Comment
Starts when detecting invalid
FADD, FSUB, FMUL, FDIV, FMAC,
operation exception defined by FCMP/EQ, FCMP/GT, FLOAT, FTRC,
IEEE754, division-by-zero
FCNVDS, FCNVSD, FSQRT
exception, overflow, underflow, or
inexact exception.
Rev. 2.00 Mar. 14, 2008 Page 1782 of 1824
REJ09B0290-0200