SH7263 Datasheet, PDF (305/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
WTRC[1:0]* 00
R/W Number of Idle Cycles from REF Command/Self-
Refresh Release to ACTV/REF/MRS Command
Specify the number of minimum idle cycles in the
periods shown below.
• From the issuance of the REF command until the
issuance of the ACTV/REF/MRS command
• From releasing self-refresh until the issuance of the
ACTV/REF/MRS command.
The setting for areas 2 and 3 is common.
00: 2 cycles
01: 3 cycles
10: 5 cycles
11: 8 cycles
Note: * If both areas 2 and 3 are specified as SDRAM, WTRP[1:0], WTRCD[1:0], TRWL[1:0],
and WTRC[1:0] bit settings are used in both areas in common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or SRAM with byte selection.
Rev. 2.00 Mar. 14, 2008 Page 271 of 1824
REJ09B0290-0200