SH7263 Datasheet, PDF (1245/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 24 AND/NAND Flash Memory Controller (FLCTL)
24.3.11 Data FIFO Register (FLDTFIFO)
FLDTFIFO is used to read or write the data FIFO area.
In DMA transfer, data in this register must be specified as the destination (source). When
transferring 16-byte DMA, access FLDTFIFO from the address on the 16-byte address boundary.
Note that the direction of read or write specified by the SELRW bit in FLCMDCR must match
that specified in this register. When changing the read/write direction, FLDTFIFO should be
cleared by setting the AC0CLR bit in FLINTDMACR before use.
Bit: 31
Initial value: -
R/W: R/W
30
-
R/W
29
-
R/W
28
-
R/W
27
-
R/W
26
-
R/W
25
-
R/W
24 23
DTFO[31:16]
-
-
R/W R/W
22
-
R/W
21
-
R/W
20
-
R/W
19
-
R/W
18
-
R/W
17
-
R/W
16
-
R/W
Bit: 15
Initial value: -
R/W: R/W
14
-
R/W
13
-
R/W
12
-
R/W
11
-
R/W
10
-
R/W
9
-
R/W
8
7
DTFO[15:0]
-
-
R/W R/W
6
-
R/W
5
-
R/W
4
-
R/W
3
-
R/W
2
-
R/W
1
-
R/W
0
-
R/W
Initial
Bit
Bit Name Value
R/W
31 to 0 DTFO[31:0] H'xxxxxxxx R/W
Description
Data FIFO Area Read/Write Data
In write: Data is written to the data FIFO area.
In read: Data in the data FIFO area is read.
Rev. 2.00 Mar. 14, 2008 Page 1211 of 1824
REJ09B0290-0200