SH7263 Datasheet, PDF (27/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

24.3.2 Command Control Register (FLCMDCR).......................................................... 1194
24.3.3 Command Code Register (FLCMCDR) ............................................................. 1197
24.3.4 Address Register (FLADR) ................................................................................ 1198
24.3.5 Address Register 2 (FLADR2) ........................................................................... 1200
24.3.6 Data Counter Register (FLDTCNTR)................................................................. 1201
24.3.7 Data Register (FLDATAR)................................................................................. 1202
24.3.8 Interrupt DMA Control Register (FLINTDMACR) ........................................... 1203
24.3.9 Ready Busy Timeout Setting Register (FLBSYTMR) ....................................... 1209
24.3.10 Ready Busy Timeout Counter (FLBSYCNT)..................................................... 1210
24.3.11 Data FIFO Register (FLDTFIFO)....................................................................... 1211
24.3.12 Control Code FIFO Register (FLECFIFO) ......................................................... 1212
24.3.13 Transfer Control Register (FLTRCR)................................................................. 1213
24.4 Operation ......................................................................................................................... 1214
24.4.1 Access Sequence................................................................................................. 1214
24.4.2 Operating Modes................................................................................................. 1215
24.4.3 Register Setting Procedure.................................................................................. 1216
24.4.4 Command Access Mode ..................................................................................... 1217
24.4.5 Sector Access Mode............................................................................................ 1222
24.4.6 ECC Error Correction ......................................................................................... 1224
24.4.7 Status Read ......................................................................................................... 1225
24.5 Interrupt Sources.............................................................................................................. 1227
24.6 DMA Transfer Specifications .......................................................................................... 1228
Section 25 USB 2.0 Host/Function Module (USB) .........................................1229
25.1 Features............................................................................................................................ 1229
25.2 Input/Output Pins ............................................................................................................. 1231
25.3 Register Description......................................................................................................... 1233
25.3.1 System Configuration Control Register (SYSCFG) ........................................... 1235
25.3.2 System Configuration Status Register (SYSSTS)............................................... 1237
25.3.3 Device State Control Register (DVSTCTR) ....................................................... 1239
25.3.4 Test Mode Register (TESTMODE) .................................................................... 1243
25.3.5 FIFO Port Configuration Registers (CFBCFG, D0FBCFG, D1FBCFG) ........... 1245
25.3.6 FIFO Port Registers (CFIFO, D0FIFO, D1FIFO) .............................................. 1248
25.3.7 FIFO Port Select Registers (CFIFOSEL, D0FIFOSEL, D1FIFOSEL)............... 1249
25.3.8 FIFO Port Control Registers (CFIFOCTR, D0FIFOCTR, D1FIFOCTR) .......... 1253
25.3.9 FIFO Port SIE Register (CFIFOSIE) .................................................................. 1255
25.3.10 Transaction Counter Registers (D0FIFOTRN, D1FIFOTRN)............................ 1256
25.3.11 Interrupts Enable Register 0 (INTENB0) ........................................................... 1257
25.3.12 Interrupt Enabled Register 1 (INTENB1) ........................................................... 1260
25.3.13 BRDY Interrupts Enable Register (BRDYENB) ................................................ 1262
Rev. 2.00 Mar. 14, 2008 Page xxvii of xxxiv
REJ09B0290-0200