SH7263 Datasheet, PDF (1470/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 27 Sampling Rate Converter (SRC)
Table 27.2 Alignment of Data before Sampling Rate Conversion
IED
ch0[15:8]
ch0[7:0]
ch1[15:8]
0
SRCID[31:24]
SRCID[23:16]
SRCID[15:8]
1
SRCID[23:16]
SRCID[31:24]
SRCID[7:0]
ch1[7:0]
SRCID[7:0]
SRCID[15:8]
27.2.2 SRC Output Data Register (SRCOD)
SRCOD is a 32-bit read-only register used to output the data after sampling rate conversion. The
data in 8-stage output data FIFO is read through SRCOD.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
The data in SRCOD is aligned differently depending on the OCH and OED bit setting in
SRCODCTRL. Table 27.3 shows the correspondence between the OCH and OED bit setting and
data alignment in SRCOD.
Table 27.3 Alignment of Data in SRCOD
OCH OED SRCOD[31:24] SRCOD[23:16] SRCOD[15:8]
0
0
ch0[15:8]
ch0[7:0]
ch1[15:8]*²
1
ch0[7:0]
ch0[15:8]
ch1[7:0]*²
1*¹
0
ch1[15:8]
ch1[7:0]
ch0[15:8]
1
ch1[7:0]
ch1[15:8]
ch0[7:0]
Notes: 1. When processing monaural data, do not set the bit to 1.
2. When processing monaural data, the data in these bits is invalid.
SRCOD[7:0]
ch1[7:0]*²
ch1[15:8]*²
ch0[7:0]
ch0[15:8]
Rev. 2.00 Mar. 14, 2008 Page 1436 of 1824
REJ09B0290-0200