SH7263 Datasheet, PDF (437/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
0
DE
0
R/W DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and
DME bit in DMAOR to 1. In this case, all of the bits
TE, NMIF in DMAOR, and AE must be 0. In an
external request or peripheral module request, DMA
transfer starts if DMA transfer request is generated by
the devices or peripheral modules after setting the
bits DE and DME to 1. If the DREQ signal is detected
by low/high level in external request mode, or in
peripheral module request mode, the NMIF bit and
the AE bit must be 0 if the TEMASK bit is 1. If the
TEMASK bit is 0, the TE bit must also be 0. If the
DREQ signal is detected by a rising/falling edge in
external request mode, all of the bits TE, NMIF, and
AE must be 0 as in the case of auto request mode.
Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note: * Only 0 can be written to clear the flag after 1 is read.
Rev. 2.00 Mar. 14, 2008 Page 403 of 1824
REJ09B0290-0200