SH7263 Datasheet, PDF (1759/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 35 Electrical Characteristics
CKIO
A25 to A0
A12/A11^*1
Tp
Tpw
Trr
Trc
Trc
t_AD1
t_AD1
t_AD1
t_AD1
CSn
RD/WR
RASU/L
CASU/L
t_CSD1
t_CSD1
t_CSD1
t_CSD1
t_RWD1
t_RWD1
t_RASD1
t_RASD1
t_RASD1
t_RASD1
t_CASD1
t_CASD1
Trc
t_RWD1
DQMxx
D31 to D0
(Hi-Z)
BS
CKE
(High)
DACKn
TENDn*²
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn and TENDn is when active low is specified.
Figure 35.36 Synchronous DRAM Auto-Refreshing Timing
(WTRP = 1 Cycle, WTRC = 3 Cycles)
Rev. 2.00 Mar. 14, 2008 Page 1725 of 1824
REJ09B0290-0200