SH7263 Datasheet, PDF (1352/1862 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7260 Series

Section 25 USB 2.0 Host/Function Module (USB)
(5) Control Transfer Stage Transition Interrupt
Figure 25.7 shows a diagram of how this module handles the control transfer stage transition. This
module controls the control transfer sequence and generates control transfer stage transition
interrupts. Control transfer stage transition interrupts can be enabled or disabled individually using
INTENB0. The transfer stage that made a transition can be confirmed using the CTSQ bit in
INTSTS0.
The control transfer sequence errors are described below. If an error occurs, the PID bit in
DCPCTR is set to B'1x (STALL).
1. During control read transfers
⎯ At the IN token of the data stage, an OUT or PING token is received when there have been
no data transfers at all.
⎯ An IN token is received at the status stage
⎯ A packet is received at the status stage for which the data packet is DATAPID = DATA0
2. During control write transfers
⎯ At the OUT token of the data stage, an IN token is received when there have been no ACK
response at all
⎯ A packet is received at the data stage for which the first data packet is DATAPID =
DATA0
⎯ At the status stage, an OUT or PING token is received
3. During no-data control transfers
⎯ At the status stage, an OUT or PING token is received
At the control write transfer stage, if the number of receive data exceeds the wLength value of the
USB request, it cannot be recognized as a control transfer sequence error. At the control read
transfer status stage, packets other than zero-length packets are received by an ACK response and
the transfer ends normally.
When a CTRT interrupt occurs in response to a sequence error (SERR = 1), the CTSQ = 110 value
is retained until CTRT = 0 is written from the system (the interrupt status is cleared). Therefore,
while CTSQ = 110 is being held, the CTRT interrupt that ends the setup stage will not be
generated even if a new USB request is received. (This module retains the setup stage end, and
after the interrupt status has been cleared by software, a setup stage end interrupt is generated.)
Rev. 2.00 Mar. 14, 2008 Page 1318 of 1824
REJ09B0290-0200